Workshop on Compilers and Tools for Constrained Embedded Systems

Held in conjunction with CASES'03 Oct. 29 - Nov. 1, 2003, San Jose, CA

Embedded systems differ from general-purpose systems in constraints such as unit and development costs, time-to-market, real-time operation, I/O with the outside world, memory size, power and energy consumption, reliability and maintainability. Fortunately the designer typically has extensive knowledge of the application code which the system will run. An elegantly designed embedded system will use this application information to optimize for the most important constraints while trading off performance in less critical areas. The compiler, OS (if present) and run-time systems are important because cycle counts determine clock speeds; using a faster processor raises design, component and debugging costs.

Advanced compilers and software analysis tools can leverage application knowledge to trade off among the constraining factors present, even enabling hardware to software migration. These tools can also extract and display otherwise buried application characteristics, providing a clear view and freeing the system designer from tedious manual analysis or transformation. The designer can then provide suggestions to the compiler, improving its performance.

Debugging embedded systems is different from debugging desktop code because of the interaction between the real-time aspects and the complexity of the inputs, which must be repeatable yet are often dependent upon system outputs. User I/O is often sharply limited, obscuring the system state. Sharp tools will simplify development and debugging, reducing time-to-market and making code much more maintainable.

One goal of this workshop is to provide a forum for investigating ways of sharpening currently blunt compilers and software tools, enabling them to do precisely what the user needs with minimal effort. A related goal is to identify those research challenges facing designers of embedded systems (low- through high-end) which could benefit from advanced compilation methods and software tools. To this end we solicit papers from industry describing current challenges, whether "grand" or "bland" -- solutions are optional, and papers need not be full length.

Submitted papers must present original, significant research which is unpublished and not submitted elsewhere. Papers should be submitted electronically through the listed website in PDF format. Shortened papers (4-6 pages) may be submitted for review; please describe any changes anticipated for the final version. Final papers should be no more than 12 single-spaced pages, with 1 inch margins and 10 point font. Author affiliations should be included on the first page of the paper with a 300 word abstract. All accepted papers will be presented at the workshop and included in informal proceedings that will be distributed at the workshop. In addition, accepted papers will be made available on the workshop home page. We plan to invite authors of selected papers to submit revised, extended versions of their papers for inclusion in a special issue of the Journal of Instruction Level Parallelism.
*There is an automatic one week extension to September 10.

Submissions *

Sep 3, 2003

Author Notif.

Sep 29, 2003

Final Paper Due

Oct 8, 2003

Workshop

Oct 29, 2003