CTCES04 Workshop

The Latham Hotel, Washington D.C., USA
Sept. 22, 2004

Final Program

 

Wednesday, Sept 22, (8am - 6pm) 

  Breakfast (on your own)
 
08:30 - 10:15      CTCES session I:  Program Analysis, Scheduling and Compression (Four 26 min talks)
 
  1. Applying Scalable Interprocedural Pointer Analysis to Embedded Applications
    Hilllery C. Hunter, Erik M. Nystrom and Wen-mei W. Hwu – University of Illinois, Urbana-Champaign, USA
  2. Echo Technology for Memory Constrained CISC Processors
    Youfeng Wu, Mauricio Breternitz Jr, Herbert Hum, Ramesh Peri and Jay Pickett -- Intel Laboratories, Santa Clara, CA, USA
  3. A Lightweight Instruction Scheduling Algorithm for Just-In-Time Compiler on XScale
    Xiaohua Shi and Peng Guo -- Intel Microprocessor Technology Laboratory, China
  4. A Branch and Bound Algorithm for Power-Aware Instruction Scheduling of VLIW Architectures
    Shu Xiao and Edmund M-K. Lai -- Nanyang Technological University, Singapore 
 
  Coffee Break
 
10:45 - 12:30      CTCES session II: System Development and Reconfigurable Architectures (Four 26 min talks)
 
  1. Constant Execution Time Recording for Replay of Sporadic Real-Time Systems
    Joel Huselius and Henrik Thane -- Malardalen University,   Vasteras, Sweden
  2. Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures
    Phillip Jones, Shobana Padmanabhan, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang,   Roger Chamberlain, Ron K. Cytron, Jason Fritts, and   John W. Lockwood -- Washington University, St. Louis, USA
  3. Compiler Techniques for Field Modifiable Architectures
    Kenshu Seto, Kojima Yoshihisa and Masahiro Fujita -- University of Tokyo, Japan
  4. Automatic and Optimized Generation of Compiled High-Speed RTL Simulators
    Alexey Kupriyanov, Frank Hannig, Jurgen Teich -- University of Erlangen-Nuremberg, Germany